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  fn6396 rev 1.00 page 1 of 27 august 10, 2010 fn6396 rev 1.00 august 10, 2010 isl8112 high light-load efficiency, dual-output, main power supply cont rollers datasheet isl8112 is a dual-output synchronous buck controller with 2a integrated driver. it features hi gh light load efficiency which is especially preferred in systems c oncerned with high efficiency in wide load range, like the ba ttery powered system. isl8112 includes two constant on-time p wm controllers. either of the two outputs can operate in output fixed mode or adjustable mode. in fixed mode, one out put can be 5v or 3.3v and the other can output 1.5v or 1.05v . in output adjustable mode, one output can be 0.7v to 5.5v, and the other output can range from 0v to 2.5v (sensing output voltage directly) or up to 5v (using resistor divider voltage for voltage sensing). thi s device also features a linear regulator providing 3.3v/5v, or adjustable from 0.7v to 4.5v via ldoref. the linear regulator provides up to 100ma output current with automatic linear-regulator bootstrapping to the byp input. when in switch over, the ldo outpu t can source up to 200ma. isl8112 includes on-board po wer-up sequencing, the power- good (pgood_) outputs, digital s oft-start, and internal soft- stop output discharge that pre vents negative voltages on shutdown. isl8112 is implemented with con stant on-time pwm control scheme which need no sense re sistors and provides 100ns response to load transients while maintaining a relatively constant switching frequency . the unique ultrasonic pulse- skipping mode maintains th e switching frequency above 25khz, eliminating undesired audible noises in low frequency operation at light load. other f eatures include pulse skipping which maximizes efficiency in light-load applications, and fixed-frequency pwm mode which reduces rf interference in sensitive applications. features ? wide input voltage range 5.5v to 25v ? constant on-time control with 100ns load-step response ? dual fixed outputs of 1.05v (3.3v) and 1.5v (5.0v), or adjustable outputs of 0.7v to 5.5v (smps1) and 0v to 2.5v/5v (smps2), 1.5% accuracy ? adjustable switching frequency: 400/500khz, 300/400khz, 200/300khz ? very high light load eff iciency (skip mode) ? 5mw quiescent power dissipation ? 1.5% (ldo): 100ma, 200ma (switch over) ? 3.3v reference vo ltage 2.0%: 5ma ? 2.0v reference voltage 1.0%: 50a ? temperature compensated r ds(on) current sensing ? programmable current limi t with foldback capability ? selectable pwm, skip or ultrasonic mode ? independent pgood1 and pgood2 comparators ? soft-start with pre-bias ed output and soft-stop ? 1.7ms digital soft-star t and independent shutdown ? independent enable ? thermal shutdown ? extremely low components count ? pb-free available (rohs compliant) applications ? power supply for telecom/datacom and pol ? system requiring high efficiency in wide load range ? compact design with minimum components count ? pdas and mobile communication devices ? 3- and 4-cell li+ batt ery-powered devices ? ddr1, ddr2, and ddr3 applications ordering information part number (note) part marking temp. range (c) package pkg. dwg. # ISL8112IRZ* isl8112 irz -40 to +100 32 ld qfn (pb-free) l32.5x5b *add -t suffix for tape and reel. please refer to tb347 for d etails on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach mat erials, and 100% matte tin plate plus anneal (e3 termination finish, wh ich is rohs compliant and compatible with both snpb and pb-free solder ing operations). intersil p b-free products are msl classified at pb -free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020.
isl8112 fn6396 rev 1.00 page 2 of 27 august 10, 2010 pinout isl8112 (32 ld 5x5 qfn) top view out2ref ilim2 vsen2 mode pgood2 en2 ug2 ph2 byp vsen1 fb1 ilim1 pgood1 en1 ug1 ph1 vref1 fs vcc en_ldo vref2 vin ldo ldoref boot2 lg2 pgnd gnd nc pvcc lg1 boot1 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516
isl8112 fn6396 rev 1.00 page 3 of 27 august 10, 2010 absolute voltage ratings thermal information vin, en_ldo to gnd . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +27v boot_ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot_ to ph_ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v vcc, en_, mode, fs, pvcc, pgood_ to gnd . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v ldo, fb1, out2ref, ldoref to gnd . . . . -0.3v to (vcc+0.3v) vsen_, vref2, vref1 to gnd . . . . . . . . . . . -0.3v to (vcc+ 0.3v ug_ to ph_ . . . . . . . . . . . . . . . . . . . . . . . . . -0 .3v to (pvcc + 0.3v) ilim_ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to (vcc + 0.3v) lg_, byp to gnd . . . . . . . . . . . . . . . . . . . . -0.3v t o (pvcc + 0.3v) pgnd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to + 0.3v ldo, vref1, vref2 short c ircuit to gnd . . . . . . . . . . cont inuous vcc short circuit to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1s ldo current (internal regulator) continuous . . . . . . . . . . . . 100ma ldo current (switched over to vsen1) continuous . . . . . +200m a thermal resistance (typical, note 1) ? ja (c/w) ? jc (c/w) 32 ld qfn (notes 1, 2) . . . . . . . . . . . . 32 3.0 operating temperature range . . . . . . . . . . . . . . . .-40 c to +100c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c storage temperature range . . . . . . . . . . . . . . . . . .-6 5c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 2. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. electrical specifications circuit of figure 17, and figure 18, no load on ldo, vsen1, vse n2, vref2, and vref1, vin = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. parameter conditions min (note 3) typ max (note 3) units main smps controllers v in input voltage range ldo in regulation 5.5 25 v v in = ldo, vsen1 < 4.43v 4.5 5.5 v 3.3v output voltage in fixed mode v in = 5.5v to 25v, out2ref > (vcc - 1v), mode = 5v 3.285 3.330 3.375 v 1.05v output voltage in fixed mode v in = 5.5v to 25v, 3.0 < out2ref < (vcc - 1.1v), mode = 5v 1.038 1.05 1.062 v 1.5v output voltage in fixed mode v in = 5.5v to 25v, fb1 = vcc, mode = 5v 1.482 1.500 1.518 v 5v output voltage in fixed mode v in = 5.5v to 25v, fb1 = gnd, mode = 5v 4.975 5.050 5.125 v fb1 in output adjustable mode v in = 5.5v to 25v 0.693 0.700 0.707 v out2ref in output adjustable mode v in = 5.5v to 25v 0.7 2.50 v smps1 output voltage adjust range smps1 0.70 5.50 v smps2 output voltage adjust range smps2 0.50 2.50 v smps2 output voltage accuracy (referred for out2ref) out2ref = 0.7v to 2.5v, mode = vcc -1.0 1.0 % dc load regulation either smps, mode = vcc, 0a to 5a -0.1 % either smps, mode = vref1, 0a to 5a -1.7 % either smps, mode = gnd, 0a to 5a -1.5 % line regulation either smps, 6v < v in < 24v 0.005 %/v current-limit current source temperature = +25c 4.75 5 5.25 a ilim_ adjustment range 0.2 2 v current-limit threshold (positi ve, default) ilim_ = vcc, gnd - p h_ (no temperature compensation) 93 100 107 mv
isl8112 fn6396 rev 1.00 page 4 of 27 august 10, 2010 current-limit threshold (positive, adjustable) gnd - ph_ vilim_ = 0.5v 40 50 60 mv vilim_ = 1v 93 100 107 mv vilim_ = 2v 185 200 215 mv zero-current threshold mode = gnd, vref1, or open, gnd - ph_ 3 mv current-limit threshold (negativ e, default) mode = vcc, gnd - ph_ - 120 mv soft-start ramp time zero to full limit 1.7 ms operating frequency (vfs = gnd), mode = vcc smps 1 400 khz smps 2 500 khz (vfs = vref1 or open), mode = vcc smps 1 400 khz smps 2 300 khz (vfs = vcc), mode = vcc smps 1 200 khz smps 2 300 khz on-time pulse width vfs = gnd (400khz/500khz) vsen1 = 5.00v 0.895 1 .052 1.209 s vsen2 = 3.33v 0.475 0.555 0.635 s vfs = vref1 or open (400khz/300khz) vsen1 = 5.05v 0.895 1.052 1.209 s vsen2 = 3.33v 0.833 0.925 1.017 s vfs = vcc (200khz/300khz) vsen1 = 5.05v 1.895 2.105 2.315 s vsen2 = 3.33v 0.833 0.925 1.017 s minimum off-time 200 300 400 ns maximum duty cycle vfs = gnd vsen1 = 5.05v 88 % vsen2 = 3.33v 85 % vfs = vref1 or open vsen1 = 5.05v 88 % vsen2 = 3.33v 91 % vfs = vcc vsen1 = 5.05v 94 % vsen2 = 3.33v 91 % ultrasonic skip operating frequency mode = vref1 or open 25 37 khz internal regulator and reference ldo output voltage byp = gnd, 5.5v < v in < 25v, ldoref < 0.3v, 0 < ildo < 100ma 4.925 5.000 5.075 v ldo output voltage byp = gnd, 5.5v < v in < 25v, ldoref > (vcc-1v), 0 < ildo < 100ma 3.250 3.300 3.350 v ldo output in adjustable mode v in = 5.5v to 25v, v ldo =2xv ldoref 0.7 4.5 v ldo output accuracy in adjustable mode v in = 5.5v to 25v, v ldoref = 0.35v to 0.5v 2 % v in = 5.5v to 25v, v ldoref = 0.5v to 2.25v 1.5 % ldoref input range v ldo =2xv ldoref 0.35 2.25 v ldo output current byp = gnd, v in = 5.5v to 25v (note 4) 100 ma ldo output current during switch over byp = 5v, v in = 5.5v to 25v, ldoref < 0.3v 200 ma ldo output current during switch over to 3.3v byp = 3.3v, v in = 5.5v to 25v, ldoref > (vcc-1v) 100 ma ldo short-circuit current ldo = gnd, byp = gnd 200 400 ma undervoltage-lockout fault threshold rising edge of pvcc falling edge of pvcc 3.9 4.35 4.05 4.5 v electrical specifications circuit of figure 17, and figure 18, no load on ldo, vsen1, vse n2, vref2, and vref1, vin = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) parameter conditions min (note 3) typ max (note 3) units
isl8112 fn6396 rev 1.00 page 5 of 27 august 10, 2010 ldo 5v bootstrap switch threshold to byp rising edge at byp regu lation point ldoref = gnd 4.53 4.68 4.83 v ldo 3.3v bootstrap switch threshold to byp rising edge at byp re gulation point ldoref = vcc 3.0 3.1 3.2 v ldo 5v bootstrap switch equivalent resistance ldo to byp, byp = 5v, ldoref > (vcc-1v) (note 4) 0.7 1.5 ? ldo 3.3v bootstrap switch equivalent resistance ldo to byp, byp = 3.3v, ldoref < 0.3v (note 4) 1.5 3.0 ? vref2 output voltage no external load, vcc > 4.5v 3.235 3.300 3.365 v no external load, vcc < 4.0v 3.220 3.300 3.380 v vref2 load regulation 0 < iload < 5ma 10 mv vref2 current limit vref2 = gnd 10 17 ma vref1 output voltage no external load 1.980 2.000 2.020 v vref1 load regulation 0 < iload < 50a 10 mv vref1 sink current vref1 in regulation 10 a v in operating supply current both smpss on, fb1 = mode = gnd, out2ref = vcc vsen1 = byp = 5.3v, vsen2 = 3.5v 25 50 a v in standby supply current v in = 5.5v to 25v, both smpss off, en_ldo = vcc 180 250 a v in shutdown supply current v in = 4.5v to 25v, en1=en2=en_ldo=0v 20 30 a quiescent power consumption both smpss on, fb1 = mode = gnd, out2ref = vcc, vsen1 = byp = 5.3v, vsen2 = 3.5v 57mw fault detection overvoltage trip threshold fb1 wi th respect to nominal regulati on point +8 +11 +14 % out2ref with respect to nominal regulation point +12 +16 +20 % overvoltage fault propagation delay fb1 or out2ref delay with 50 mv overdrive 10 s pgood_ threshold fb1 or out2ref with respect to nominal output, falling edge, typical hysteresis = 1% -12-9-6% pgood_ propagation delay falling edge, 50mv overdrive 10 s pgood_ output low voltage isink = 4ma 0.2 v pgood_ leakage current high state, forced to 5.5v 1 a thermal-shutdown threshold +150 c output undervoltage shutdown threshold fb1 or out2ref with respe ct to nominal output voltage 65 70 75 % output undervoltage shutdown blanking time from en_ signal 10 20 30 ms inputs and outputs fb1 input voltage low level 0.3 v high level vcc-1.0 v out2ref input voltage vsen2 dynamic range, vsen2= v out2ref 0.5 2.50 v fixed vsen2 = 1.05v 3.0 vcc- 1.1 v fixed vsen2 = 3.3v vcc-1.0 v electrical specifications circuit of figure 17, and figure 18, no load on ldo, vsen1, vse n2, vref2, and vref1, vin = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) parameter conditions min (note 3) typ max (note 3) units
isl8112 fn6396 rev 1.00 page 6 of 27 august 10, 2010 ldoref input voltage fixed ldo = 5v 0.30 v vsen2 dynamic range, v ldo =2xv ldoref 0.35 2.25 v fixed ldo = 3.3v vcc-1.0 v mode input voltage low level (skip) 0.8 v float level (ultrasonic skip) 1.7 2.3 v high level (pwm) 2.4 v fs input voltage low level 0.8 v float level 1.7 2.3 v high level 2.4 v en1, en2 input voltage clear fault level/smps off level 0.8 v delay start level 1.7 2.3 v smps on level 2.4 v en_ldo input voltage rising edge 1.2 1.6 2.0 v falling edge 0.94 1.00 1.06 v input leakage current vfs = 0 or 5v -1 +1 a ven _ = ven_ldo = 0v or 5v -0.1 +0.1 a vmode = 0v or 5v -1 +1 a vfb1 = 0v or 5v -0.2 +0.2 a vrefin = 0v or 2.5v -0.2 +0.2 a vldoref = 0v or 2.75v -0.2 +0.2 a internal boot diode v d forward voltage pvcc - v boot , i f = 10ma 0.65 0.8 v i boot_leakage leakage current v boot = 30v, ph = 25v, pvcc = 5v 500 na mosfet drivers ug_ gate-driver sink/source c urrent ug1, ug2 forced to 2v 2 a lg_ gate-driver source current l g1 (source), lg2 (source), forc ed to 2v 1.7 a lg_ gate-driver sink current lg 1 (sink), lg2 (sink), forced to 2 v3.3a ug_ gate-driver on-resistance bst_ - ph_ forced to 5v (note 4) 1 .5 4.0 ? lg_ gate-driver on-resistance lg_, high state (pull-up) (note 4) 2.2 5.0 ? lg_, low state (pull-down) (note 4) 0.6 1.5 ? dead time lg_ rising 15 20 35 ns ug_ rising 20 30 50 ns vsen1, vsen2 discharge on resistance 25 40 ? notes: 3. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established b y characterization and are not production tested. 4. limits established by characte rization and are not production tested. electrical specifications circuit of figure 17, and figure 18, no load on ldo, vsen1, vse n2, vref2, and vref1, vin = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) parameter conditions min (note 3) typ max (note 3) units
isl8112 fn6396 rev 1.00 page 7 of 27 august 10, 2010 pin descriptions pin name function 1 vref1 2v reference output. bypass to gnd with a 0.1f (min) capa citor. vref1 can source up to 50 ? a for external loads. loading vref1 degrades fb and output accuracy according to the vref1 load-regulation error. 2 fs frequency select input. connect to gnd for 400khz/500khz oper ation. connect to vref1 (or leave open) for 400khz/300khz operation. connect t o vcc for 200khz/300khz opera tion (5v/3.3v smps switching frequencies, respectively). 3 vcc analog supply voltage for pwm core. bypass to gnd with a 1f ceramic capacitor. 4 en_ldo ldo enable input. the ldo is enabled if en_ldo is within logic high level and vin is h igher than por threshold. the ldo is disabled if en_ldo is l ess than the logic low level. 5 vref2 3.3v reference output. vref2 can source up to 5ma for exte rnal loads. bypass to gnd with a 0.01f capacitor if loaded. leave open if there is no load. 6 vin power-supply input. vin is used for the constant-on-time pwm on-time one-shot circuits. vin is also used to power the linear regulators. the linear regulators are powered by smps1 i f vsen1 is set greater than 4.78v and byp is tied to vsen1. connect vin to the battery input and bypass with a 1f c apacitor. 7 ldo linear-regulator output. ldo can provide a total of 100ma ex ternal loads. the ldo regul ate at 5v if ldoref is connected to gnd. when the ldo is set at 5v and byp is within 5 v switch over threshold, the internal regulator shuts down and the ldo output pin connects to byp through a 0.7 ? switch. the ldo regulate at 3.3v if ldoref is connected to vcc. when the ldo is set at 3.3v and byp is within 3.3v switch over threshold, the internal regulator shuts down and the ldo output pin connects to byp through a 1.5 ? switch. bypass ldo output with a minimum of 4.7f ceramic. 8 ldoref ldo reference input. connec t ldoref to gnd for fixed 5v o peration. connect ldoref to vcc for fixed 3.3v operation. ldoref can be used to program ldo output voltage fro m 0.7v to 4.5v. ldo output is two times the voltage of ldoref. there is no switch over in adjustable mode. 9 byp byp is the switch over source voltage for the ldo when ldore f connected to gnd or vcc. connect byp to 5v if ldoref is tied to gnd. connect byp to 3.3v if ldoref is tied to vcc. the byp is also controlled by en_ldo. when ldorefin is tied to gnd, the byp is not switched over to ldo un til smps1 finished soft-starting. 10 vsen1 smps1 output voltage-sense input. connect to the smps1 out put. vsen1 is an input to the constant on-time-pwm on-time one-shot circuit. it als o serves as the smps1 feedback input in fixed-voltage mode. 11 fb1 smps1 feedback input. connect fb1 to gnd for fixed 5v operat ion. connect fb1 to vcc for fixed 1.5v operation connect fb1 to a resistive volt age-divider from vsen1 to gnd to adjust the output from 0.7v to 5.5v. 12 ilim1 smps1 current-limit adjustment. the gnd-ph1 current-limit threshold is 1/10th the voltage seen at ilim1 over a 0.2v to 2v range. there is an internal 5a current source from vcc t o ilim1. connect ilim1 to vref1 for a fixed 200mv threshold. the logic current l imit threshold is default to 100m v value if ilim1 is higher than vcc - 1v. 13 pgood1 smps1 power-good open-drai n output. pgood1 is low when th e smps1 output voltage is more than 10% below the normal regulation point or during soft-start. pgo od1 is high im pedance when the output is in regulation and the soft- start circuit has terminated . pgood1 is low in shutdown. 14 en1 smps1 enable input. the smps1 is enabled if en1 is greater t han the logic high level and disabled if en1 is less than the logic low level. if en1 is connected to vref1, the smps1 st arts after the smps2 reaches regulation (delay start). drive en1 below 0.8v to clear fa ult level and reset the fault l atches. 15 ug1 high-side mosfet floating gate-driver output for smps1. ug1 swings between ph1 and boot1. 16 ph1 inductor connection for smps1. p h1 is the internal lower sup ply rail for the ug1 high-si de gate driver. ph1 is the current-sense input for the smps1. 17 boot1 boost flying capacitor connection for smps1. connect to an external capacitor accordi ng to the typical application circuits (figure 17 and figure 18) . see mosfet gate drivers (u g_, lg_) on page 19. 18 lg1 smps1 synchronous-rectifier g ate-drive output. lg1 swings be tween gnd and pvcc. 19 pvcc pvcc is the supply voltage for the low-side mosfet driver l g_. connect a 5v power source to the pvcc pin (bypass with 1f mlcc capacitor to pgnd if necessary). there is interna l 10 ? pfet connecting pvcc to vcc. make sure that both vcc and pvcc are bypassed with 1f mlcc capacitors. 20 nc no connection pin. exter nally connect it to ground. 21 gnd analog ground for both smps_ and ldo. connect externally to the underside of the exposed pad. 22 pgnd power ground for smps_ controller. connect pgnd externally to the underside of the exposed pad.
isl8112 fn6396 rev 1.00 page 8 of 27 august 10, 2010 pin name function 23 lg2 smps2 synchronous-rectifier g ate-drive output. lg2 swings be tween gnd and pvcc. 24 boot2 boost flying capacitor connection for smps2. connect to an external capacitor accordi ng to the typical application circuits (figure 17 and figure 18) . see mosfet gate drivers (u g_, lg_) on page 19 . 25 ph2 inductor connection for smps2. p h2 is the internal lower sup ply rail for the ug2 high-si de gate driver. ph2 is the current-sense input for the smps2. 26 ug2 high-side mosfet floating gate-driver output for smps2. ug1 swings between ph2 and boot2. 27 en2 smps2 enable input. the smps2 is enabled if en2 is greater t han the logic high level and disabled if en2 is less than the logic low level. if en2 is connected to vref1, the smps2 st arts after the smps1 reaches regulation (delay start). drive en2 below 0.8v to clear fa ult level and reset the fault l atches. 28 pgood2 smp2 power-good open-drain output. pgood2 is low when the smps2 output voltage is more than 10% below the normal regulation point or during soft-start. pgo od2 is high im pedance when the output is in regulation and the soft- start circuit has terminated . pgood2 is low in shutdown. 29 mode low-noise mode control. connec t mode to gnd for normal idle -mode (pulse-skipping) operation or to vcc for pwm mode (fixed frequency). c onnect to vref1 or leave floating for ultrasonic skip mode operation. 30 vsen2 smps2 output voltage-sense input. connect to the smps2 out put. vsen2 is an input to the constant on-time-pwm on-time one-shot circuit. it als o serves as the smps2 feedback input in fixed-voltage mode. 31 ilim2 smps2 current-limit adjustment. the gnd-ph1 current-limit threshold is 1/10th the voltage seen at ilim2 over a 0.2v to 2v range. there is an internal 5a current source from vcc t o ilim2. connect ilim2 to vref1 for a fixed 200mv. the logic current limit threshold is default to 100mv value if ilim2 is higher than vcc - 1v. 32 out2ref output voltage control for smps2. connect out2ref to vcc for fixed 3.3v. connect out 2ref to vref2 for fixed 1.05v. out2ref can be used to program smps2 output. vsen2 equal s out2ref from 0.5v to 2.50v. smps2 output voltage is 0v if out2ref < 0.5v. pin descriptions (continued) typical performance curves circuit of figure 17 and figure 18, no load on ldo, vsen1, vsen 2, vref2, and vref1, v in = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. figure 1. v out2 = 1.05v efficiency vs load (300khz) figure 2. v out1 = 1.5v efficiency vs load (200khz) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.001 0.010 0.100 output load (a) efficiency 1.000 7 v in skip mode 7 v in pwm mode 7 v in ultra skip mode 12 v in skip mode 12 v in pwm mode 25 v in skip mode 25 v in pwm mode 25 v in ultra skip mode 12 v in ultra skip mode 10.000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.010 0.100 1.000 10.000 output load (a) efficiency 0.001 7 v in skip mode 7 v in pwm mode 7 v in ultra skip mode 12 v in skip mode 12 v in pwm mode 25 v in skip mode 25 v in pwm mode 25 v in ultra skip mode 12 v in ultra skip mode
isl8112 fn6396 rev 1.00 page 9 of 27 august 10, 2010 figure 3. v out2 = 3.3v efficiency vs load (500khz) figure 4. v out1 = 5v efficiency vs load (400khz) figure 5. v out2 = 1.05v frequency vs load figure 6. v out2 = 1.05v ripple vs load figure 7. v out1 = 1.5v frequency vs load figure 8. v out1 = 1.5v ripple vs load typical performance curves circuit of figure 17 and figure 18, no load on ldo, vsen1, vsen 2, vref2, and vref1, v in = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.001 0.010 0.100 1.000 10.000 output load (a) efficiency 7 v in skip mode 7 v in pwm mode 7 v in ultra skip mode 12 v in skip mode 12 v in pwm mode 25 v in skip mode 25 v in pwm mode 25 v in ultra skip mode 12 v in ultra skip mode 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.001 0.010 0.100 1.000 10.000 output load (a) efficiency 7 v in skip mode 7 v in pwm mode 7 v in ultra skip mode 12 v in skip mode 12 v in pwm mode 25 v in skip mode 25 v in pwm mode 25 v in ultra skip mode 12 v in ultra skip mode 0 50 100 150 200 250 300 0.001 0.010 0.100 1.000 10.000 output load (a) pwm ultra-skip skip frequency (khz) 0 5 10 15 20 25 30 35 40 45 50 0.001 0.010 0.100 1.000 10.000 output load (a) ripple (mv) pwm ultra-skip skip 0 50 100 150 200 250 0.001 0.010 0.100 1.000 10.000 output load (a) frequency (khz) pwm ultra-skip skip 0 5 10 15 20 25 30 35 40 45 50 0.001 0.010 0.100 1.000 10.000 output load (a) ripple (mv) pwm ultra-skip skip
isl8112 fn6396 rev 1.00 page 10 of 27 august 10, 2010 figure 9. v out2 = 3.3v frequency vs load figure 10. v out2 = 3.3v ripple vs load figure 11. v out1 = 5v frequency vs load figure 12. v out1 = 5v ripple vs load figure 13. ldo output 5v vs load figure 14. ldo output 3.3v vs loa d typical performance curves circuit of figure 17 and figure 18, no load on ldo, vsen1, vsen 2, vref2, and vref1, v in = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) 0 100 200 300 400 500 600 0.001 0.010 0.100 1.000 10.000 output load (a) frequency (khz) pwm ultra-skip skip 0 2 4 6 8 10 12 14 0.001 0.010 0.100 1.000 10.000 output load (a) ripple (mv) pwm skip ultra-skip 0 50 100 150 200 250 300 350 400 450 0.001 1.000 output load (a) frequency (khz) 10.000 skip ultra-skip pwm 0.010 0.100 0 5 10 15 20 25 30 35 40 0.001 0.010 0.100 1.000 10.000 output load (a) ripple (mv) pwm skip ultra-skip 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 0 50 100 150 200 output load (ma) output voltage (v) byp = 0v byp = 5v 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 0 50 100 150 200 output load (ma) output voltage (v) byp = 3.3v byp = 0v
isl8112 fn6396 rev 1.00 page 11 of 27 august 10, 2010 typical application circuits the typical application circuits are shown in figures 17, 18 an d 19. in figure 17, the power supp ly system generates 1.25v/5a and dynamic voltage/10a. f igure 18 shows system having1.5v/5a and 1.05v/5a output. the input supply range is 5.5v to 25v. figure 19 shows system having1.2v/15a and 2.5v/5a output. the input supp ly range is 5.5v to 25v and 4.5v to 5.5v respectively. detailed description the isl8112 dual-buck, bicm os, switch-mode power-supply controller generates logic s upply voltages for notebook computers. the isl8112 is desi gned primarily for battery- powered applications wher e high efficiency and low-quiescent supply current are critical. the isl8112 provides a pin- selectable switching frequency, allowing operation for 200khz/300khz, 400khz/300kh z, or 400khz/500khz on the smpss. light-load efficiency is enhan ced by automatic idle-mode operation, a variable-frequency pulse-skipping mode that reduces transition and gate-cha rge losses. each step-down, power-switching circuit consists of two n-channel mosfets, a rectifier, and an lc output fil ter. the output voltage is the average ac voltage at the switching node, which is regulated by changing the duty cycle of t he mosfet switches. the gate- drive signal to the n-channel h igh-side mosfet must exceed the battery voltage, and is provi ded by a flying-capacitor boos t circuit that uses a 100nf cap acitor connected to boot_. both smps1 and smps2 pwm cont rollers consist of a triple- mode feedback network and multi plexer, a multi-input pwm comparator, high-side and low-si de gate drivers and logic. in addition, smps2 can also use out2ref to track its output from 0.5v to 2.50v. the isl8112 contains fault-protection circuits that monitor the main pwm outputs for undervoltage and overvoltage conditions. a power-on sequence block controls the power-up timing o f the main pwms and monitors the outputs for undervoltage fa ults. the isl8112 includes an adjustable low drop-out linear r egulator. the bias generator blocks include the linear regula tor, 3.3v precision reference, 2v precision reference and aut omatic bootstrap switch over circuit. the synchronous-switch gate drivers are directly powered from pvcc, while the high-side switch gate drivers are indirectly powered from pvcc through an external capacitor and an internal schottky diode boost circuit. an automatic bootstrap circui t turns off the ldo linear regulator and powers the device from byp if ldoref is set to gnd or vcc. see table 1. free-running, constant on-time pwm controller with input feed-forward the constant on-time pwm c ontrol architecture is a pseudo-fixed-frequency, constan t on-time, current-mode type with voltage feed forward. the constant on-time pwm control architecture relies on the output ripple voltage to provide the pwm ramp signal; thus the output filt er capacitor's esr acts figure 15. standby input current vs v in (en = en2 = 0, en_ldo = vcc) figure 16. shutdown input current vs v in (en = en2 = en_ldo = 0) typical performance curves circuit of figure 17 and figure 18, no load on ldo, vsen1, vsen 2, vref2, and vref1, v in = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) 173.0 173.5 174.5 175.0 175.5 176.0 176.5 177.0 177.5 7 9 11 13 15 17 19 21 23 25 input voltage (v) input current (a) 174.0 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 26.0 26.5 7 9 11 13 15 17 19 21 23 25 input voltage (v) input current (a) table 1. ldo output voltage table ldo voltage conditions comment voltage at byp ldoref < 0.3v, byp > 4.63v internal ldo is disabled. voltage at byp ldoref > vcc - 1v, byp > 3v internal ldo is disabled. 5v ldoref < 0.3v, byp < 4.63v internal ldo is active. 3.3v ldoref > vcc - 1v, byp < 3v internal ldo is active. 2 x ldoref 0.35v isl8112 fn6396 rev 1.00 page 12 of 27 august 10, 2010 as a current-feedback resistor. the high-side switch on-time is determined by a one-sho t whose period is inversely proportional to input voltage and directly proportional to output voltage. another one-s hot sets a minimum off-time (300ns typ). the on-time on e-shot triggers when the following conditions are met: t he error comparator's output is high, the synchronous rectifier current is below the current- limit threshold, and the minimum off time one-shot has timed out. on-time one-shot (fs) each pwm core includes a one- shot that sets the high-side switch on-time for each contro ller. each fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to batte ry and output voltage. the high-side switch on-time is inversely prop ortional to the battery voltage as measured by the v in input and proportional to the output voltage. this algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. the benefit of a const ant switching frequency is that the frequency ca n be selected to avoi d noise-sensitive frequency regions: see table 2 for approximate k- factors. switching frequency increases as a function of load current due to the increasing drop across the synchronous rectifier, which causes a faster inductor-current discharge r amp. on-times translate only roughly to switching frequenci es. the on-times guaranteed in the electrical characteristi cs are influenced by switching delays in the external high-s ide power mosfet. also, the dead-time effect increases the effective on-time, reducing the switching frequ ency. it occurs only in pwm mode (mode = vcc) and during dynamic output voltage transitions when the inductor c urrent reverses at light or negative load currents. with reversed inductor current, the inductor's emf causes ph_ to go high earlier than normal, extending the on-time by a per iod equal to t he ug-rising dead time. for loads above the critical conduction point, the actual switching frequency is: where: ?v drop1 is the sum of the parasit ic voltage drops in the inductor discharge path, incl uding synchronous rectifier, inductor, and pc board resistances ?v drop2 is the sum of the parasitic voltage drops in the charging path, including high-side switch, inductor, and pc board resistances ?t on is the on-time calculated by the isl8112. t on kv out i load r dson lowerq ?? ? + ?? v in --------------------------------------------------------------- -------------------------------------- - = (eq. 1) f v out v drop1 + t on v in v drop2 + ?? ------------------------------------------------------- = (eq. 2) table 2. approximate k-factor errors smps switching frequency (khz) k-factor (s) approximate k-factor error (%) (fs = gnd, vref1, or open), vsen1 400 2.5 10 (fs = gnd), vsen2 500 2.0 10 (fs = vcc), vsen1 200 5.0 10 (fs = vcc, vref1, or open), vsen2 300 3.3 10
isl8112 fn6396 rev 1.00 page 13 of 27 august 10, 2010 ldo boot2 ug2 ph2 lg2 pgnd vsen2 out2ref en2 vin boot1 ug1 ph1 lg1 vsen1 agnd fb1 ilim1 mode en1 en_ldo vin: 5.5v to 25v out2-gfx track out2ref/10a out1 C pci-e q1 irf7821 q2 irf7832 l2: 2.2h l1: 3.3h q3a si4816bdy q3b c1 10 c2 2 x 330f c4 0.22f r3 200k ? c10 10f c11 330f 6.3v vcc c5 isl8112 vcc 1.25v/5a c1 10f c2 4m ? 6.3v c9 c11 9m ? vcc ldoref fs fb1 tied to gnd = 5v fb1 tied to vcc = 1.5v out2ref tied to vref2 = 1.05v out2ref tied to vcc = 3.3v pvcc c8 1f byp nc out2ref: dynamic 0 to 2.5v gnd 5v 2 bits dac 5v ilim2 vref2 pgood1 r5 open vcc c3 r4 pgood2 r6 vcc 200k ? 0.1f c7 vref1 pad r2 10k ? r1 7.87k ? nc gnd - + - + - + droop vcc + + 1f vcc 200k ? 200k ? frequency-dependent components 1.25v/1.05v smps switching frequency fs = vcc 200khz/300khz l1 3.3h l2 2.7h c2 2 x 330f c11 330f 0.1f figure 17. isl8112 typical dynamic gfx application circuit
isl8112 fn6396 rev 1.00 page 14 of 27 august 10, 2010 ldo boot2 ug2 ph2 lg2 pgnd vsen2 out2ref en2 vin boot1 ug1 ph1 lg1 vsen1 agnd fb1 ilim1 mode en1 en_ldo vin: 5.5v to 25v out2 1.05v/5a out1 q1a l2: 2.2f l1: 3.3h q3a si4816bdy q3b c1 10 f ldo c2 330f c4 0.22f r3 200k ? c6 4.7f c10 10f c11 33f 6.3v vcc c5 isl8112 vcc 1.5v/5a c1 10 c2 4m ? 6.3v f c9 0.1f c11 9m ? on off on off off vcc ldoref fs fb1 tied to gnd = 5v out2ref tied to vref2 = 1.05v out2ref tied to vcc = 3.3v pvcc c8 1f byp ldoref tied to gnd = 5v ldoref tied to vcc = 3.3v nc out2ref: dynamic 0 to 2.5v vcc 5v vcc 3.3v ilim2 vref2 pgood1 r5 0.01f vcc c3 r4 pgood2 r6 vcc 200k ? 200k ? 200k ? 0.1f c7 vref1 pad vcc si4816bdy vref2 vcc q1b fb1 tied to vcc = 1.5v frequency-dependent components 1.5v/1.05v smps switching frequency fs = vcc 200khz/300khz l1 3.3h l2 2.7h c2 330f c11 330f 1f figure 18. isl8112 typical system regulator application circuit
isl8112 fn6396 rev 1.00 page 15 of 27 august 10, 2010 frequency-dependent components 1.2v/2.5v smps switching frequency fs = gnd 400khz/500khz l1 1.5h l2 1.5h c2 3x330f c11 330f vin: 4.5v to 5.5v 1.2v/15a q1 irf7821 q2 irf7832 l1: 1.5h l2: 1.5h q3a si4816bdy q3b c1 10 f c2 3 x 330f c4 0.22f r3 200k c10 10 f c11 330f 6.3v c5 1 vcc 2.5v/5a c1 10 f c2 4mo 6.3v ? c9 0.1f f c11 9mo f vcc ldoref fb1 tied to gnd=5v fb1 tied to vcc=1.5v out2ref tied to vref3=1.05v out2ref tied to vcc=3.3v c8 1f out2ref: dynamic 0 to 2.5v gnd vcc r5 open vcc c3 r4 r6 vcc 225ko 225ko 225ko 0.1f c7 r2 43ko r1 110ko nc gnd r7 1o vcc r8 73ko r9 110ko gnd ref ldo boot2 ug2 ph2 lg2 pgnd vsen2 out2ref en2 vin boot1 ug1 ph1 lg1 vsen1 agnd fb1 ilim1 mode en1 en_ldo vcc isl8112 pvcc byp nc ilim2 vref2 pgood1 pgood2 vref1 pad fs vin: 4.5v to 5.5v 1.2v/15a q1 irf7821 q2 irf7832 l1: 1.5h l2: 1.5h q3a si4816bdy q3b c1 10 f c2 3 x 330f c4 0.22f r3 200k c10 10 f c11 330f 6.3v c5 1 vcc 2.5v/5a c1 10 f c2 4mo 6.3v ? c9 0.1f f c11 9mo f vcc ldoref fb1 tied to gnd=5v fb1 tied to vcc=1.5v out2ref tied to vref3=1.05v out2ref tied to vcc=3.3v c8 1f out2ref: dynamic 0 to 2.5v gnd vcc r5 open vcc c3 r4 r6 vcc 225ko 225ko 225ko 0.1f c7 r2 43ko r1 110ko nc gnd r7 1o vcc r8 73ko r9 110ko gnd ref ldo boot2 ug2 ph2 lg2 pgnd vsen2 out2ref en2 vin boot1 ug1 ph1 lg1 vsen1 agnd fb1 ilim1 mode en1 en_ldo vcc isl8112 pvcc byp nc ilim2 vref2 pgood1 pgood2 vref1 pad fs figure 19. isl8112 typical system regulator application circuit ldoref vref1 vref2 fb1 tied to vcc=1.5v ? ? ? ? ? ? ? ? ? ?
isl8112 fn6396 rev 1.00 page 16 of 27 august 10, 2010 power-on squence clear fault latch smps1 synch. pwm buck en1 pgood1 en2 pgood2 boot1 boot2 ug2 lg2 pgnd out2ref vsen2 pgood1 ug1 ph1 ph2 lg1 fb1 vsen1 - + ldo vin en_ldo en1 fs ilim2 vref2 thermal shutdown gnd power-on sequence clear fault latch vref1 vref2 pvcc - + - + ldo pvcc ilim1 thermal shutdown ldoref pgood2 vsen1 sw thres. vcc 10 ? byp mode vref1 vsen2 pvcc internal logic controller smps2 synch. pwm buck controller en2 figure 20. detail functional diagram isl8112 vcc ldo m1
isl8112 fn6396 rev 1.00 page 17 of 27 august 10, 2010 automatic pulse-skipping switch over (idle mode) in idle mode (mode = gnd), an inherent autom atic switch over to pfm takes place at li ght loads. this switch over is affected by a comparator that trun cates the low-side switch on- time at the inductor current's zero crossing. this mechanism causes the threshol d between pulse-skipping pfm and non- skipping pwm operation to coi ncide with the boundary between continuous and disc ontinuous inductor-current operation (also known as the critical conduction point): where k is the on-time scale fa ctor (see on-time one-shot (fs) on page 12). the load-cu rrent level at which pfm/pwm crossover occurs, i load(skip) , is equal to half the peak-to-peak ripple current, which is a function of the inducto r value (figure 22). for example, in the isl8112 typical application circuit with vout1 = 5v, v in = 12v, l = 7.6h, and k = 5s, switch over to pulse- skipping operation occurs at i load = 0.96a or about on-fifth full load. the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. figure 22. ultrasonic current waveforms the switching waveforms may appear noisy and asynchronous when light loading causes pulse -skipping operation, but this is a normal operating condition t hat results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency a re made by varying the inductor va lue. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming t hat the coil resistance remains fi xed) and less output voltage ripple. penalties for using higher inductor values include larg er + mode + + + vin r s q q + + + a + s r q q + + + pgood_ fault latch to lg_ driver ilim_ vsen_ + comp + + vin r s q r s q trig min. t off one shot q + + + s + + s r q s r q q + slope comp fb_ + + + + + 20ms to ug_driver vsen_ fs ph_ vcc 5a boot_ boot uv detect fb decoder vref + out2ref (smps2) q ov_latch_ uv_latch_ fault latch logic blanking 0.9v ref 1.1v ref 0.7v ref figure 21. pwm controller (one side only) i load skip ?? kv out ? 2l ? ------------------------ v in v out C v in ------------------------------- - = (eq. 3) on-time 0time i peak l v in -v out i t = inductor current i load = /2 i peak l v in -v i i peak l v in -v ? i i peak l v in -v i i peak
isl8112 fn6396 rev 1.00 page 18 of 27 august 10, 2010 physical size and degraded load-transient response (especially at low input-voltage levels). dc output accuracy spec ifications refer to the trip level of th e error comparator. when the inductor is in continuous conduction, the output voltage h as a dc regulation higher than the trip level by 50% of the ri pple. in discontinuous conductio n (mode = gnd, light load), t he output voltage has a dc regulation higher than the trip level by approximately 1.0% due to slope compensation. forced-pwm mode the low-noise, forced-pwm (mode = vcc) mode disables the zero-crossing comparator, which controls the low-side switch on-time. disabling the zero-cro ssing detector causes the low- side, gate-drive waveform to become the complement of the high-side, gate-drive waveform. the inductor current reverses at light loads as the pwm loop s trives to maintain a duty ratio of v out / v in . the benefit of forced- pwm mode is to keep the switching frequency fairly constant, but it comes at a cost: th e no-load battery curr ent can be 10ma to 5 0ma, depending on switching frequency and t he external mosfets. forced-pwm mode is mos t useful for reducing audio-frequency noise, improving load-transient response, providing sink-current capabili ty for dynamic output voltage adjustment, and improving the cross-regulation of multiple-output applicat ions that use a fly back transformer or coupled inductor. enhanced ultrasonic mode (25khz (min) pulse skipping) leaving mode unconnected or connecting mode to vref1 activates a unique pulse-s kipping mode wit h a minimum switching frequency of 25khz. th is ultrasonic pulse-skipping mode eliminates audio-frequ ency modulation that would otherwise be presen t when a lightly loaded controller automatically skips pul ses. in ultrasonic mode, the controller automatically transitions to fixed-frequency pwm operation when the load reaches the same critical conduction point (iload(skip)). an ultrasonic pulse occurs when the controller detects that no switching has occurr ed within the last 20s. once triggered, the ultrasonic controller pulls l g high, turning on the low-sid e mosfet to induce a negative indu ctor current. after fb drops below the regulation point, the c ontroller turns off the low-si de mosfet (lg pulled low) and tri ggers a constant on-time (ug driven high). when the on-time has expired, the controller re- enables the low-side mosfet until the controller detects that the inductor current dropped below the zero-crossing threshold. starting with a lg pulse greatly reduces the peak output voltage when compared to starting with a ug pulse, as long as vfb < vref, lg is off a nd ug is on, si milar to pure skip mode. reference and linear regulators (vref2, vref1, and ldo) the 3.3v reference (vref2) is accurate to 1.5% over temperature, making vref2 us eful as a precision system reference. vref2 can supply up to 5ma for ex ternal loads. bypass vref2 to gnd with a 0.01 f capacitor. leave open if there is no load. the 2v reference (vref1) is accurate to 1% over temperature, also making vref1 useful as a precision system reference. bypass vref1 to gnd with a 0.1f (min) capacitor. vref1 can supply up to 50a for external loads. an internal regulator produces a fixed 5v (ldoref < 0.2v) or 3.3v (ldoref > vcc - 1v). in an adjustable mode, the ldo output can be set from 0.7v to 4.5v. the ldo output voltage is equal to two times the ldoref voltage. the ldo regulator can supply up to 100ma for external loads. bypass ldo with a minimum 4.7f ceramic capa citor. when the ldoref < 0.2v and byp voltage is 5v, the ldo bootstrap- switch over to an internal 0.7 ? p-channel mosfet switch connects byp to ldo pin while simultaneously shutting down the internal linear regulator. these actions bootst rap the device, powering the loads from the byp input voltages, rather than through internal linear regulators from the bat tery. similarly, when the byp = 3.3v and ldoref = vcc, the ldo bootstrap-switch over to an internal 1.5 ? p-channel mosfet switch connects byp to ldo pin while simult aneously shutting down the internal linear regulator. no swit ch over action in adjustable mode. current-limit circuit (ilim_) with r ds(on) temperature compensation the current-limit circuit emplo ys a "valley" current-sensing algorithm. the isl8112 uses the on-resistance of the synchronous rectifier as a current-sensing element. if the magnitude of the current-sense signal at ph_ is above the current-limit threshold, the pwm is not allowed to initiate a n ew cycle. the actual peak current is greater than the current-limi t fb isl8112 fn6396 rev 1.00 page 19 of 27 august 10, 2010 threshold by an amount equal t o the inductor ripple current. therefore, the exact c urrent-limit characteristic and maximum load capability are a function of the current-limit threshold, inductor value and inpu t and output voltage. for lower power dissipation, the isl8112 uses the on-resistance of the synchronous rectifier as the current-sense element. use the worst-ca se maximum value for r ds(on) from the mosfet data sheet. add so me margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.5% additional resistance for each c of temperature rise. the isl8112 controller has a built-i n 5a current source as shown in figure 25. place the hottest power mosefts as close to the ic as possible for best thermal coupling. the current limit varies with the on-resistance o f the synchronous rectifier. when combined with the undervolt age-protection circuit, this current-limit method is effective in almost every circumstance. figure 25. current limit block diagram a negative current limit preve nts excessive reverse inductor currents when vout sinks curren t. the negative current-limit threshold is set to approximatel y 120% of the positive current limit and therefo re tracks the positive c urrent limit when ilim _ is adjusted. the current-limit th reshold is adjusted with an external resistor for isl8112 at ilim_. the current-limit threshold adjustment range is from 20mv to 200mv. in the adjustable mode, the current-lim it threshold voltage is 1/10th the voltage at ilim_. the volt age at ilim pin is the product of 5a * r ilim . the threshold defaults to 100mv when ilim_ is connected to vcc. th e logic threshold fo r switch-over to the 100mv default value is approximately vcc - 1v. the pc board layout g uidelines should be carefully observed to ensure that noise and dc erro rs do not corrupt the current- sense signals at ph_. mosfet gate drivers (ug_, lg_) the ug_ and lg_ gate drivers sink 2.0a and 3.3a respectively of gate drive, ensuring robust gate drive for high-current applications. the ug_ floating high-side mosfet drivers are powered by diode-capacitor charge pumps a t boot_. the lg_ synchronous-rectifier dr ivers are powered by pvcc. the internal pull-down transis tors that drive lg_ low have a 0.6 ? typical on-resistance. these low on-resistance pull-down transistors prevent lg_ from bei ng pulled up during the fast rise time of the inductor node s due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mosfets. however, for high-current applications, some combinations of high- and lo w-side mosfets may cause excessive gate-drain coupling, which leads to poor efficiency and emi-producing shoot-thro ugh currents. adding a 4.7 ? resistor in series with boot_ increases the turn-on time of the high-side mosfets at the expe nse of efficiency, without degrading the turn-off time (figure 26). time i limit i load i peak i load(max) 2 ) ( i i i load val lim ? = ? i time i limit i load i peak i load(max) ( i i lim i i limit i load i peak i load(max) ( i i lim i limit i load i peak i load(max) ( i i lim - i inductor current figure 24. valley current limit threshold point + to current limit logic ilim_ + vcc 5a r 9r r ilim + + v ilim + ilim_ + vcc r 9r + + 5v q1 vin out_ c boot 4.7 ? boot_ q1 vin 5v q1 vin q1 vin ug_ ph_ isl8112 pvcc figure 26. reducing the switching-node rise time
isl8112 fn6396 rev 1.00 page 20 of 27 august 10, 2010 adaptive dead-time circuits monitor the lg_ and ug_ drivers and prevent either fet from turn ing on until the other is fully off. this algorithm allows opera tion without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be low-resistance, low-inductance paths from the gate drivers to the m osfet gates for the adaptive dead-time circuit to work pr operly. otherwise, the sense circuitry interprets the mosfet gate as "off" when there is actually charge left on the gate . use very short, wide traces measuring 10 to 20 squares (50 mils to 100 mils wide if the mosfet is 1 fro m the device). boost-supply capacitor selection (buck) the boost capacitor s hould be 0.1f to 4 .7f, depending on the input and output voltages, e xternal components, and pc board layout. the boost capaci tance should be as large as possible to prevent it from charging to excessive voltage, but small enough to adequately c harge during the minimum low-side mosfet conduction time, which happens at maximum operating duty cycle (t his occurs at minimum input voltage). the minimum gate to source voltage (v gs(min) ) is determined by: where: ? pvcc is 5v ?c gs is the gate capacitance of the high-side mosfet por, uvlo, and intern al digital soft-start power-on reset (por) occu rs when vin rises above approximately 3v. uvlo occurs when pvcc drops below approximately 4v. t he vin por reset the ldo control. the uvlo resets the undervoltage, overvoltage, and thermal- shutdown fault latches. pvcc undervoltage lockout (uvlo) circuitry inhibits switching when pvcc is below 4v. lg_ is low during uvlo. the output voltages begin to ramp up once pvcc exceeds its 4v uvlo and vref1 is in regulation. the internal digital soft-start timer begins to ramp up the m aximum-allowed current limit during start-up. the 1.7ms ramp occurs in five st eps of positive current limit and the step size is 20%, 40%, 60%, 80% and 100%. power-good output (pgood_) the pgood_ comparator conti nuously monitors both output voltages for undervoltage conditions. pgood_ is actively held low in shutdown, standby, and soft-start. pgood1 releases and digital soft-start terminates when vsen1 reach the error- comparator threshold. pgood1 goes low if vout1 output turns off or is 10% below its nominal regulation point. pgood1 is a true open-drain output. likewis e, pgood2 is used to monitor vsen2. fault protection the isl8112 provides overvoltage/undervoltage fault protection in the buck cont rollers. once activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions. ? out-of-bound condition when the output volt age is 5% above the set voltage, the out-of-bound condition activa tes. lg turns on until output reaches within regulation. once the output is within regulation, the controller will operate as normal. it is the "f irst line of defense" before ovp. ? overvoltage protection when vsen1 is 11% (16% for vsen2) above the set voltage, the overvoltage faul t protection activates. this latches on the synchronous rectifier mosf et with 100% duty cycle, rapidly discharging the output capac itor until the negative current limit is achi eved. once negative current limit is met, ug is turned on for a minimum on-time, followed by another lg pulse until negative curr ent limit. this effectively regulates the disc harge current a t the negative current limit in an effort to pr event excessively large negativ e currents that cause potentiall y damaging negative voltages on the load. once an overvoltage fault condition is set, it can only be reset by toggling shdn#, en_, or cycling pvcc(uvlo). ? undervoltage protection when the output voltage drops b elow 70% of its regulation voltage for at least 100s, the c ontroller sets the fault latch and begins the discharge m ode (see the shutdown and output discharge sect ion). uvp is ignored for at least 20ms (typical), after start-up or aft er a rising edge on en_. toggle en_ or cycle pvcc (uvlo) to clear the undervoltage fault latch and restart the controller. uvp only applies to the buck outputs. ? thermal protection the isl8112 has thermal shut down to protect the devices from overheating. thermal sh utdown occurs when the die temperature exceeds +150c. a ll internal circuitry shuts down during thermal shutdow n. the isl8112 may trigger thermal shutdown if ldo_ i s not bootstrapp ed from vsen_ while applying a high input vol tage on vin and drawing the maximum current (incl uding short circuit) from ldo_. even if ldo_ is bootstrapped from vsen _, overloading the ldo_ causes large power dissipation on the bootstra p switches, which may result in thermal shutdown. cycling en_, en_ldo, or pvcc(uvlo) ends the thermal-shutdown state. v gs min ?? pvcc c boot c boot c gs + --------------------------------------- ? = (eq. 4)
isl8112 fn6396 rev 1.00 page 21 of 27 august 10, 2010 discharge mode (soft-stop) when a transition to standby o r shutdown mode occurs, or the output is discharged to g nd through an internal 25 ? switch, the reference remains active t o provide an accurate threshold and to provide overvo ltage protection. when the output undervoltage faul t latch is set , both channels are discharged to gnd th rough the internal 25 ? switches. shutdown mode the isl8112 smps1, smps2 and ldo have independent enabling control. drive en1 , en2 and en_ldo below the precise input falling-edge trip l evel to place the isl8112 in i ts low-power shutdown state. the isl8112 consumes only 20a of quiescent current while in shutdown. when shutdown mode activates, the 3.3v vref2 remai n on. both smps outputs are discharged to 0v through a 25 ? switch. power-up sequencing and on/off controls (en_) en1 and en2 control smps pow er-up sequencing. en1 or en2 rising above 2.4v enables t he respective outputs. en1 or en2 falling below 1.6v disabl es the respective outputs. connecting en1 or en2 to vre f1 will force its outputs off while the other output is below regul ation. the sequenced smps will start once the other s mps reaches regulation. the second smps remains on until the first smps turns off, the device shuts down, a fault occurs or pvcc goes into undervoltage lockout. both supplies begin their power-down sequence immediately wh en the first supply turns off. driving en_ below 0.8v clear s the overvoltage, undervoltage and thermal fault latches. table 3. operating-mode truth table mode condition comment power-up pvcc < uvlo threshold. tr ansitions to discharge mode aft er a pvcc uvlo and after vref1 becomes valid. ldo, vref2, and vref1 remain active. run en_ldo = high, en1 or en2 enabled. normal operation overvoltage protection either output > 111% (vsen1) or 116% (vsen2) of nominal level. lg_ is forced high. ldo, vref2 and vref1 active. exited by a pv cc uvlo, vcc por, or by toggling en1 or en2. undervoltage protection either output < 70% of nominal after 20ms time-out expires and output is enabled. both the internal 25 switches turn on. ldo, vref2 and vref1 ar e active. exited by a pvcc uvlo, or by toggling en1 or en2. discharge either smps output is still high in either standby mode or shutdown mode discharge switch (25 ? ) connects vsen_ to gnd. one output may still run while the other is in discharge mode. activates when pvcc is in uvlo, or transition to uvlo, standby, or shutdown has begun. ldo, vref2 and vref1 active. standby en1, en2 < startup threshold, en_ldo= high ldo, vref2 and vref1 active. shutdown en1, en2, en_ldo = low discharge switch (25 ? ) connects vsen_ to pgnd. all circuitry off except vref2. thermal shutdown tj > +150c all circuitry off. exited by pvcc uv lo or cycling en_. vref2 remain active. table 4. shutdown and standby control logis ven_ldo ven1 (v) ven2 (v) ldo smps1 smps2 low low low off off off >2.5 ? high low low on off off >2.5 ? high high high on on on >2.5 ? high high low on on off >2.5 ? high low high on off on >2.5 ? high high vref1 on on on (after smps1 is up) >2.5 ? high vref1 high on on (after smps2 is up) on
isl8112 fn6396 rev 1.00 page 22 of 27 august 10, 2010 adjustable-output feedback (dual-mode fb) connect fb1 to gnd to enable t he fixed 5v or tie fb1 to vcc to set the fixed 1.5v output. c onnect a resistive voltage-divid er at fb1 between out put and gnd to adjus t the respective output voltage between 0.7v and 5.5v (figure 27). choose r2 to be approximately 10k and solve for r 1 using equation 5. where v fb1 = 0.7v nominal. figure 27. setting v out1 with a resistor divider likewise, connect out2ref to v cc to enable the fixed 3.3v or tie out2ref to vref2 to set the fixed 1.05v output. set out2ref from 0 to 2.50v for smps2 tracking mode (figure 28). where: ? vr = 2v nominal (if tied to vref1) or ? vr = 3.3v nominal (if tied to vref2) design procedure establish the input voltage r ange and maximum load current before choosing an inductor and its associated ripple-current ratio (lir). the following four fa ctors dictate the rest of the design: 1. input voltage range. the maximum value ( v in (max)) must accommodate the maximum ac adapter voltage. the minimum value ( v in (min)) must account for the lowest input voltage after drops due to c onnectors, fuses and battery selector switches. lower input voltages result in better efficiency. 2. maximum load current. the peak load current (iload(max)) determines the instantaneous component stress and filtering requirem ents and thus drives output capacitor selecti on, inductor saturation rating and the design of the curre nt-limit circuit. t he continuous load current (iload) determines t he thermal stress and drives the selection of input cap acitors, mosfe ts and other critical heat-contributing components. 3. switching frequency. this ch oice determines the basic trade-off between size and efficiency. the optimal frequency is largely a functi on of maximum input voltage and mosfet switching losses. 4. inductor ripple current ratio ( lir). lir is the ratio of the peak-peak ripple current to th e average inductor current. size and efficiency trade-of fs must be considered when setting the inductor ripple current ratio. low inductor values cause large ripple currents, r esulting in the smallest size, but poor efficiency and high output noise. the minimum practical inductor value is one that causes the circuit to operate at critical conduction (where the inductor current just touches zero with ever y cycle at maximum load). inductor values lower than th is grant no further size- reduction benefit. the isl8112 pulse-skipping algorithm (mode = gnd) initiates skip mode at the crit ical conduction point, so the inductor's operating point also determines the load current at which pwm/pfm switch over occurs. the optimum point is usually found between 20% and 50% ripple current. inductor selection the switching frequency (on- time) and operating point (% ripple or lir) determine the inductor value as follows: r1 r2 v out1 v fb1 ------------------ - 1 C ?? ?? ?? ? = (eq. 5) q3 q4 vin out1 ugate_ lgate_ isl88732 isl88733 isl88734 vout_ fb_ r1 vin ugate1 lgate1 isl6236 out1 fb1 r2 q3 q4 vin out1 ugate_ lgate_ isl88732 isl88733 isl88734 vout_ fb_ vin ug1 lg1 isl8112 vsen1 fb1 q1 q2 vin ugate_ lgate_ isl88732 isl88733 isl88734 vout_ fb_ r3 r4 q1 q2 vin out2 ugate2 lgate2 isl6236 out2 refin2 vr q1 q2 vin ugate_ lgate_ isl88732 isl88733 isl88734 vout_ fb_ r3 r4 q1 q2 vin out2 ug2 lg2 isl8112 vsen2 out2ref figure 28. setting v out2 with a voltage divider for tracking r3 r4 vr v out2 ------------------ - 1 C ?? ?? ? = (eq. 6) l v out_ v in v out_ + ?? v in fliri load max ?? ?? ? --------------------------------------------------------------- ------ = (eq. 7)
isl8112 fn6396 rev 1.00 page 23 of 27 august 10, 2010 example: i load(max) = 5a, v in =12v, v out2 =5v, f = 200khz, 35% ripple current or lir = 0.35: find a low-loss inductor havin g the lowest possible dc resistance that fits in the allo tted dimensions. ferrite cores are often the best choice. the core must be large enough not to saturate at the peak i nductor current (ipeak): the inductor ripple current als o impacts transient response performance, especially at low v in - vsen_ differences. low inductor values allow the induct or current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the p eak amplitude of the output transient (vsag) is also a functi on of the maximum duty factor, which can be calculated from the on-time and minimum off- time: where minimum off-time = 0.35 s (max) and k is from table 2. determining the current limit the minimum current- limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the valley of the inductor current occurs at iload(max) minus half of the ripple current; therefore: where: i limit(low) = minimum current-limit threshold voltage divided by the r ds(on) of q2/q4. use the worst-case m aximum value for r ds(on) from the mosfet q2/q4 data sheet and a dd some margin for the rise in r ds(on) with temperat ure. a good general rule is to allow 0.2% additional resistance for each c of temperature rise. examining the 5a circuit example with a maximum r ds(on) =5m ? at room temperature. a t +125c reveals the following: 4.17a is greater than the valley current of 4.12a, so the circu it can easily deliver the full-rat ed 5a using the 30mv nominal current-limit threshold voltage. output capacitor selection the output filter capacitor m ust have low enough equivalent series resistance (esr) to meet output ripple and load-transien t requirements, yet have high en ough esr to satisfy stability requirements. the output capacitance must also be high enough to absorb the inductor energy whi le transitioning from full-loa d to no-load conditions without tripping the overvoltage fault latch . in applications where the output is subject to large load transien ts, the output capacitor's size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: where v dip is the maximum-tolerable transient voltage drop. in non-cpu applications, the outpu t capacitor's size depends on how much esr is needed to maintain an acceptable level of output voltage ripple: where v p-p is the peak-to-peak output voltage ripple. the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacito r technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true o f tantalum, os-con, and other e lectrolytic-type capacitors). when using low-capacity filter capacitors such as polymer types , capacitor size is usually determined by the capacity required t o prevent vsag and vsoar from tripping the undervoltage and overvoltage fault latches during load transients in ultrasonic mode. for low input-to-output voltage differentials ( v in / v out < 2), additional output capacitance is required to maintain stability and good efficiency in ultrasonic mode. the amount of overshoot due to stored inductor energy can be calculated as: where i peak is the peak inductor current. input capacitor selection the input capacitors must meet t he input-ripple-current (irms) requirement imposed by the switching current. the isl8112 dual switching regulator operates at different frequencies. thi s interleaves the current pulses dr awn by the two switches and reduces the overlap time where they add together. the input rms current is much smaller in comparison than with both smpss operating in phase. the input rms curre nt varies with load and the input voltage. the maximum input ca pacitor rms current for a single smps is given by: l 5v 12v 5v C ?? 12v 200khz 0.35 5a ??? --------------------------------------------------------------- -- 8.3 ? h == (eq. 8) ipeak i load max ?? lir 2 ? ?? i load max ?? ? ?? + = (eq. 9) vsag ? i load max ?? ?? 2 lk v out_ v in ------------------ - t off min ?? + ?? ?? ?? ?? ?? ?? ? 2c out v out k v in v out C v in ------------------------------- - ?? ?? ?? - t off min ?? ?? --------------------------------------------------------------- ------------------------------------------------------------ - = (eq. 10) i limit low ?? i load max ?? lir 2 ? ?? i load max ?? ? ?? C ? (eq. 11) i limit low ?? 25mv ?? 5m ? 1.2 ? ?? 5a 0.35 2 ? ?? 5a C ? ?? ? = (eq. 12) 4.17a 4.12a ? (eq. 13) r ser v dip i load max ?? --------------------------------- - ? (eq. 14) r esr v pp C l ir i load max ?? ? ----------------------------------------------- ? (eq. 15) v soar i peak 2 l ? 2c out v out_ ?? ----------------------------------------------- - = (eq. 16) i rms i load v out v in v out_ C ?? v in ------------------------------------------------------------ ?? ?? ?? ? (eq. 17)
isl8112 fn6396 rev 1.00 page 24 of 27 august 10, 2010 when , irms has maximum current of . the esr of the input-capacitor is important f or determining capacitor power dissipation. all the power (i rms 2 x esr) heats up the capacitor an d reduces efficiency. nontantalum chemistries (ceramic or os-con ) are preferred due to their low esr and resilience to power-up surge currents. choose input capacitors that exhibit le ss than +10c temperature rise at the rms input current for optimal circuit longevity. place t he drains of the high-side switches close to each o ther to share common input bypass capacitors. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>5a) when using high-voltage (>20v) a c adapters. low-current applications usually req uire less attention. choose a high-side mosfet ( q1/q3) that has conduction losses equal to the switching lo sses at the typical battery voltage for maximum efficienc y. ensure that the conduction losses at the minimum inpu t voltage do not exceed the package thermal limits or viola te the overall thermal budget. ensure that conduction losses plus switching losses at the maximum input voltage do not e xceed the package ratings or violate the overall thermal budget. choose a synchronous rectifi er (q2/q4) wit h the lowest possible r ds(on) . ensure the gate is not pulled up by the high- side switch turning on due to parasitic drain-to-gate capacitance, causing cross-c onduction problems. switching losses are not an issue for the synchronous rectifier in the bu ck topology since it is a zero-volt age switched dev ice when using the buck topology. mosfet power dissipation worst-case conduction losses occur at the duty-factor extremes. for the high-side m osfet, the worst-case power dissipation (pd) due to the mosfet's r ds(on) occurs at the minimum battery voltage: generally, a small high-side mosfet reduces switching losses at high input vol tage. however, the r ds(on) required to stay within package power-dissi pation limits often limits how small the mosfet can be. the optimum situation occurs when the switching (ac) losses equal the conduction ( rds(on) ) losses. switching losses in the high-side mosfet can become an insidious heat problem when maximum battery voltage is applied, due to the s quared term in the cv 2 f switching-loss equation. reconsider the high-side mosfet chosen for adequate r ds(on) at low battery voltages if it becomes extraordinarily hot w hen subjected to v in(max) . calculating the power dissipa tion in nh (q1/q3) due to switching losses is difficult sin ce it must allow for quantifyi ng factors that influen ce the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source in ductance, and pc board layout characteristics. the followin g switching-loss calculation provides only a very r ough estimate and is no substitute for bench evaluation, preferably in cluding verification using a thermocouple mounted on nh (q1/q3): where c rss is the reverse transfer capacitance of q h (q1/q3) and i gate is the peak gate-driv e source/sink current. for the synchronous rectifier, the worst-case power dissipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy overlo ads that are greater than i load(max) but are not quite hi gh enough to exceed the current limit and caus e the fault latch to trip. to protect aga inst this possibility, "overdesign" the circuit to tolerate: where i limit(high) is the maximum valle y current allowed by the current-limit circuit, incl uding threshold tolerance and resistance variation. rectifier selection current circulates from gr ound to the junction of both mosfets and the inductor when the high-side switch is off. as a consequence, the polarity of the switching node is negative with respect to ground. this volt age is approximately -0.7v (a diode drop) at both transition edges while both switches are of f (dead time). the drop is when the low-side switch conducts. the rectifier is a clamp across the synchronous rectifier that catches the negative inductor swing during the dead time between turning the high-side mosfet off and the synchronous rectifier on. t he mosfets incorporate a high-speed silicon body diode as an adequate clamp diode if efficiency is not of primary impor tance. place a schottky diode in parallel with the body diode to reduce the forward voltage drop and prevent t he q2/q4 mosfet body diodes from turning on during the dead time. typically, the external diode improves the efficiency by 1% to 2%. use a schottky diode with a dc current rating equal to one-third of the load current . for example, use an mbr0530 (500ma-rated) type for loads up to 1.5a, a 1n5817 type for loads up to 3a, or a 1n5821 type for loads up to 10a. the rectifi er's rated reverse breakdown v in 2v out_ d50% = ?? ? = ? ? ?? v out_ v in min ?? ------------------------ ?? ?? ?? i load ?? 2 r ds on ?? ? = (eq. 18) pd q h switching ?? v in max ?? ?? 2 c rss f sw i load ?? i gate ---------------------------------------------------- - ?? ?? ?? = (eq. 19) pd q l ?? 1 v out v in max ?? -------------------------- C ?? ?? ?? i load 2 r ds on ?? ? = (eq. 20) i load i limit high ?? lir ?? 2 ? ?? i load max ?? ? + = (eq. 21) i l r ds on ?? ?
isl8112 fn6396 rev 1.00 page 25 of 27 august 10, 2010 voltage must be at least equal t o the maximum input voltage, preferably with a 20 % derating factor. applications information dropout performance the output voltage-adjust range for continuous-conduction operation is restricted by t he nonadjustable 350ns (max) minimum off-time one-shot. us e the slower 5v smps for the higher of the two output voltages for best dropout performance in adjustable feedback mode. t he duty-factor limit must be calculated using worst-case values for on-times and off-times, when working with low input voltages. manufacturing tolerances and internal propagat ion delays intro duce an error to the fs k-factor. also, keep in mind that trans ient-response performance of buck regulators o perated close to dropout is poor, and bulk output capacitanc e must often be added (see equation 10 on page 23). the absolute point of dropout occurs when the inductor current ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h= ? i up / ? i down indicates the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor cu rrent is less able to increase during each switch ing cycle and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value fo r h is 1.5, but this can be adjusted up or down to all ow trade-offs between v sag, output capacitance and minimum operating voltage. for a given value of h, the minimum operating vo ltage can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths ( see on-time one-shot (fs) on page 12), t off(min) is from the electrical specifications table on page 4 and k is tak en from table 2. the absolute minimum input voltage is calculated with h = 1. operating frequency must be re duced or h must be increased and output capacitance added to obtain an acceptable v sag if calculated v in(min) is greater than the required minimum input voltage. calculate v sag to be sure of adeq uate transient response if operation near dropout is anticipated. dropout design example: isl8112: with v out2 =5v, fsw= 400khz, k=2.25s, t off(min) = 350ns, v drop1 =v drop2 = 100mv, and h = 1.5, the minimum v in is: calculating with h = 1 yields: therefore, v in must be greater than 6 .65v. a practical input voltage with reasonable outp ut capacitance would be 7.5v. pc board layout guidelines careful pc board layout is critical to achieve minimal switchin g losses and clean, stable operation. this is especially true whe n multiple converters are on the same pc board where one circuit can affect the other. r efer to the isl8112 evaluation k it data sheet for a specific layout example. mount all of the power components on the top side of the board with their ground terminals fl ush against one another, if possible. follow these guidelin es for good pc board layout: ? isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. use a separate pgnd plane under the vsen1 and vsen2 sides (cal led pgnd1 and pgnd2). avoid the introduction of ac c urrents into the pgnd1 and pgnd2 ground planes. ru n the power plane ground currents on the top si de only, if possible. ? use a star ground connection on the power plane to minimize the crosstalk between vsen1 and vsen2. ? keep the high-current paths s hort, especially at the ground terminals. this practi ce is essential for stable, jitter-free operation. ? keep the power traces and lo ad connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can e nhance full-load efficiency by 1% or more. correctly routi ng pc board traces must be approached in terms of fractio ns of centimeters, where a single m ? of excess trace resistan ce causes a measurable efficiency penalty. ? ph_ (isl8112) and gnd connections to the synchronous rectifiers for current limitin g must be made using kelvin- sense connections to guarant ee the current-limit accuracy with 8-pin so mosfets. this is best done by routing power to the mosfets from outside u sing the top copper layer, while connecting ph_ traces inside (underneath) the mosfets. ? when trade-offs in trace l engths must be made, it is preferable to allow the induc tor charging path to be made longer than the discharge path. for example, it i s better to allow some extra distance betwe en the input capacitors and the high-side mosf et than to allow di stance between the inductor and the synchronous rectifier or between the inductor and the outpu t filter capacitor. ? ensure that the vsen_ connecti on to cout_ is short and direct. however, in some cas es it may be desirable to deliberately introduce some t race length between the vsen_ connector node and the ou tput filter ca pacitor (see the stability consi derations section). ? route high-speed switching nodes (boot_, ug_, ph_, and lg_) away from sensitive anal og areas (vref1, ilim_, and v in min ?? v out_ v drop + ?? 1 t off min ?? h ? k ----------------------------------- - ?? ?? C -------------------------------------------------- - v drop2 v drop1 C + = (eq. 22) v in min ?? 5v 0.1v + ?? 1 0.35 ? s1.5 ? 2.25 ? s ------------------------------- ?? ?? C ---------------------------------------------- 0.1v 0.1v 6.65v = C + = (eq. 23) v in min ?? 5v 0.1v + ?? 1 0.35 ? s1 ? 2.25 ? s -------------------------- ?? ?? C ----------------------------------------- 0.1v 0.1v 6.04v = C + = (eq. 24)
fn6396 rev 1.00 page 26 of 27 august 10, 2010 isl8112 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2006-2010. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. fb_). use pgnd1 and pgnd2 as an emi shield to keep radiated switching noise away from the ic's feedback divider and analog bypass capacitors. ? make all pin-strap contro l input connections (mode, ilim_, etc.) to gnd or vcc of the device. layout procedure place the power components first with ground terminals adjacent (q2/q4 source, cin_, cout_). if possible, make all these connections on the to p layer with wide, copper-filled areas. mount the contro ller ic adjacent to the synchronous rectifier mosfets close to the hottest spot, preferably on the back side in order to keep ug_, gnd, and the lg_ gate drive lines short and wide. the lg_ g ate trace must be short and wide, measuring 50 mils to 100 mils wide if the mosfet is 1 from the controller device. group the gate-drive componen ts (boot_ capacitor, vin bypass capacitor) together near the controller device. make the dc/dc controller gr ound connections as follows: 1. near the device, create a small analog ground plane. 2. connect the small analog ground plane to gnd and use the plane for the ground connection for the vref1 and vcc bypass capacitors, fb dividers and ilim resistors (if any). 3. create another sm all ground island for pgnd and use the plane for the vin bypass capacitor, placed very close to the device. 4. connect the gnd and pgnd planes together at the metal tab under device. on the board's top side (power planes), make a star ground to minimize crosstalk between the two sides . the top-side star ground is a star connection of the input capacitors and synchronous rectifiers. keep the resistance low between the star ground and the source of t he synchronous rectifiers for accurate current limit. conne ct the top-side star ground (used for mosfet, input, and output capacitors) to the small island with a single s hort, wide connection (preferably just a via). create pgnd islands on the layer just below the top-side layer (refer to the isl8112 ev kit for an example) to act as an emi shield if multiple layers are available (highly recommended). connect each of these individually to the star ground via, which connects the top side to the pgnd plane. add one more solid ground plane under the device to act as an additional shield, and also connect the solid ground plane to the star ground via. connect the output power p lanes (vcore and system ground planes) directly to the ou tput filter capacitor positive and negative terminals with multiple vias.
isl8112 fn6396 rev 1.00 page 27 of 27 august 10, 2010 package outline drawing l32.5x5b 32 lead quad flat no-lead plastic package rev 3, 5/10 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metalliz ed terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 32x 0.40 0.10 4 a 32x 0.23 m 0.10 c b 16 9 4x 0.50 28x 3.5 6 pin #1 index area 3 .30 0 . 15 0 . 90 0.1 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 30 ) ( 4. 80 typ ) ( 28x 0 . 5 ) (32x 0 . 23 ) ( 32x 0 . 60) + 0.07 - 0.05 17 25 24 8 1 32


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